Register files are popular components within modern processor and hardware accelerator designs. A register file is an array of registers typically comprising dedicated read and write ports; in contrast to ordinary memory which usually comprises shared read/write ports. Register files are typically implemented as small, high speed memory components, and are often required to enable sequential read and write operations within a single clock cycle. In order to achieve this, a register file is often tightly coupled to other components within the processor/accelerator design in order to enable such high speed access. Due to this need to tightly couple a register file to other components, standard memory circuits (typically random access memory (RAM)-based) are typically not appropriate. As such, it is known to implement a register file using a custom placed flip-flop implementation.
A problem with such a custom placed flip-flop implementation is that a standard flip-flop requires a relatively large silicon area and has relatively slow timing performance compared with simpler storage elements such as latches. However, in a gated latch implementation, input signal changes cause immediate changes in output when enabled. As such, when several latches follow each other using the same clock signal, signals can propagate through all of them at once. As such, a problem with a latch-based implementation is a need to resolve hold timing of signals in order to prevent an input signal causing an immediate change in output.
A further problem with the use of latches is in relation to a need to implement design for test functionality within modern integrated circuit devices. In particular, it is often required to enable scan design within register files, whereby registers in the design are connected in one or more scan chains. However, due to their inability to implement hold timing between latches, a latch-based implementation is typically not appropriate for enabling such scan chains.